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A 10.1-ENOB, 6.2-fJ/conv.-step, 500-MS/s, Ringamp-Based Pipelined-SAR ADC With Background Calibration and Dynamic Reference Regulation in 16-nm CMOS

Jorge Lagos, Nereo Markulić, Benjamin Hershberg, Davide Dermit, Mithlesh Shrivas, Ewout Martens, Jan Craninckx

2022IEEE Journal of Solid-State Circuits56 citationsDOI

Abstract

This work presents a single-channel, fully dynamic pipelined-SAR ADC with relaxed architectural tradeoffs thanks to the use of ring amplification and background calibration. It leverages a novel SAR quantizer and narrowband dither injection to achieve fast and comprehensive background calibration of DAC mismatch, interstage gain, and ring amplifier (ringamp) linearity and bias optimality. The ADC also includes an on-chip, wide-range, fully dynamic reference regulation system. Implemented in 16-nm CMOS, it consumes 3.3 mW at 500 MS/s (including regulation) and achieves 10.1 ENOB and 75.5-dB SFDR, resulting in Schreier and Walden figure-of-merit (FoM) values of 171.1 dB and 6.2 fJ/conv.-step, respectively.

Topics & Concepts

Spurious-free dynamic rangeEffective number of bitsSuccessive approximation ADCCalibrationDitherCMOSDynamic rangeLinearityFigure of meritComputer scienceElectronic engineeringNoise shapingCapacitorPhysicsElectrical engineeringEngineeringVoltageComputer visionQuantum mechanicsAnalog and Mixed-Signal Circuit DesignCCD and CMOS Imaging SensorsAdvancements in Semiconductor Devices and Circuit Design
A 10.1-ENOB, 6.2-fJ/conv.-step, 500-MS/s, Ringamp-Based Pipelined-SAR ADC With Background Calibration and Dynamic Reference Regulation in 16-nm CMOS | Litcius