Digital-to-time converter for test equipment implemented using FPGA DSP blocks

Paweł Kwiatkowski

2021Measurement24 citationsDOI Open Access PDF

Abstract

This paper presents a novel digital-to-time converter (DTC) implemented using digital signal processing (DSP) blocks built in field-programmable gate array (FPGA) devices. The converter was implemented in a low-cost Xilinx Spartan-6 FPGA chip manufactured in the 45 nm CMOS process and can be applied in any other programmable logic device that contains DSP blocks. The designed DTC time interval jitter is below 2.8 ps. This is the lowest time interval jitter so far reported in such kind of circuits implemented in a programable device. The obtained resolution of up to 8.6 ps is about twice as good as that achieved in a single carry-chain-based delay-line. Furthermore, the designed circuit saves FPGA general-purpose logic (programmable logic blocks). This kind of converter can be especially useful as a part of test instrumentations as well as time-domain signal processing systems implemented in the latest generation of programmable logic devices.

Topics & Concepts

Field-programmable gate arrayJitterDigital signal processingComputer scienceSimple programmable logic deviceProgrammable logic arrayElectronic engineeringComputer hardwareProgrammable logic deviceDigital electronicsErasable programmable logic deviceProgrammable Array LogicMacrocell arrayEmbedded systemCMOSLogic gateEngineeringLogic synthesisElectronic circuitElectrical engineeringLogic familyAdvancements in PLL and VCO TechnologiesAnalog and Mixed-Signal Circuit DesignVLSI and Analog Circuit Testing