A 205–273-GHz Frequency Multiplier Chain (×6) With 9-dBm Output Power and 1.92% DC-to-RF Efficiency in 0.13-µm SiGe BiCMOS
Zekun Li, Jixin Chen, Dawei Tang, Rui Zhou, Wei Hong
Abstract
This article presents a 205–273-GHz wideband frequency multiplier chain (FMC) in a 0.13- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> SiGe BiCMOS technology with <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$f_{\mathrm {T}}{/}f_{\mathrm {max}} =300$ </tex-math></inline-formula> /500 GHz. The proposed FMC consists of a <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$Q$ </tex-math></inline-formula> -band input transformer (TF) balun, an <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$F$ </tex-math></inline-formula> -band frequency tripler, an <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$F$ </tex-math></inline-formula> -band power amplifier (PA), and a <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$G$ </tex-math></inline-formula> -/ <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$J$ </tex-math></inline-formula> -band frequency doubler, which results in a sixth multiplier. To obtain high output power and high efficiency, a two-way power combining push–push doubler with second harmonic resonators is introduced. The high quality factor ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$Q$ </tex-math></inline-formula> -factor) cross-fingers capacitor is employed in the wideband output matching network to reduce the insertion loss (IL). A wideband PA is utilized to drive the following doubler. The frequency tripler with an adaptive bias circuit is proposed to exhibit high output power while relatively flat conversion gain (CG), with which the output power of the tripler can be easily controlled. An analysis of the input TF balun is introduced for improving the common mode rejection, which results in high even harmonic suppression of the tripler. The proposed FMC exhibits 9-dBm saturated output power ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$P_{\mathrm {sat}}$ </tex-math></inline-formula> ), with a 3-dB bandwidth of 68 GHz. The dc-to-RF efficiency of 1.92% is achieved with more than 10-dB CG at 252 GHz. The FMC consumes less than 0.5 W and occupies a small chip area. To the best of our knowledge, the proposed FMC exhibits the highest <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$P_{\mathrm {sat}}$ </tex-math></inline-formula> and dc-to-RF efficiency in silicon-based implementations beyond 200 GHz.