High Performance mm Wave AlN/GaN MISHEMTs on 200 mm Si Substrate
Sachin Yadav, A. Alian, Rana ElKashlan, Barry O’Sullivan, Ahmad Khaled, Babak Kazemi, Uthayasankaran Peralagu, Sourish Banerjee, Bertrand Parvais, Nadine Collaert
Abstract
We report high performance AlN/GaN MISHEMTs grown using MOCVD on 200 mm Si substrates with in-situ silicon nitride (Si <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</inf> N <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">4</inf> ) as the common gate insulator and access region passivation layer. The RF small and large-signal performance trade-offs of AIN and Si <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</inf> N <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">4</inf> thickness scaling are systematically examined. Ultra-thin barrier and dielectric stacks (AIN < 2.5 nm, Si <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</inf> N <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">4</inf> ≤ 2 nm) lead to excellent small-signal performance with peak f <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">max</inf> : ~190 GHz at 110 nm gate lengths but trapping induced current collapse is worsened, degrading the RF large-signal performance. For thicker stacks (AIN ≥ 2.5 nm and Si <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</inf> N <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">4</inf> ≥ 3 nm), current collapse is lower and large-signal performance improves significantly while still maintaining. f <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">max</inf> >150 GHz with good linearity. Record large-signal performance (@ 28 GHz) at 200 μm gate width is demonstrated with a P <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">SAT</inf> : 2.2 W/mm (26.8 dBm) and PAE : 55.5% at V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">d</inf> : 10 V and a P <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">SAT</inf> : 2.8 W/mm (27.5 dBm) and PAE : 54.8% at V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">d</inf> : 20 V.