Quaternary NAND Logic and Complementary Ternary Inverter with p‐MoTe<sub>2</sub>/n‐MoS<sub>2</sub> Heterostack Channel Transistors
Sam Park, Han Joo Lee, Wonjun Choi, Hye‐Jin Jin, Hyunmin Cho, Yeonsu Jeong, Sol Lee, Kwanpyo Kim, Seongil Im
Abstract
Abstract Applications of 2D semiconductors have been extensively studied, much oriented to various electron devices. Recently, multivalue field‐effect transistors (FETs) are also included among 2D‐based electron device studies in consideration that multivalue FETs may resolve power consumption issues in future integrated circuits. Several n‐channel devices are thus reported along with a few p‐channel devices, while studies to achieve both n‐ and p‐channel multivalue FETs are hardly found. Here, both n‐ and p‐channel multivalue FETs are fabricated using p‐MoTe 2 /n‐MoS 2 heterostack channel architecture, where either p‐ or n‐channel ternary value FET is reproducible by switching the stacking order of p‐ and n‐channel layer. The main ternary value mechanism originates from resonant tunneling type injection and channel inversion, which take place during device operation. For a state‐of‐the‐art device application in 2D electronics, a quaternary NAND logic circuit is for the first time demonstrated by integrating two ternary n‐channel FETs, and a complementary ternary inverter is also fabricated by integrating multivalue p‐channel and plain n‐channel FET.