Ultrascaled Double-Gate Monolayer <mml:math xmlns:mml="http://www.w3.org/1998/Math/MathML" display="inline" overflow="scroll"><mml:msub><mml:mrow><mml:mi>Sn</mml:mi><mml:mi mathvariant="normal">S</mml:mi></mml:mrow><mml:mn>2</mml:mn></mml:msub></mml:math> MOSFETs for High-Performance and Low-Power Applications
Shiying Guo, Yangyang Wang, Xuemin Hu, Shengli Zhang, Hengze Qu, Wenhan Zhou, Zhenhua Wu, Xuhai Liu, Haibo Zeng
Abstract
The shrinking of field-effect transistors (FETs) is in great demand for next-generation integrated circuits. However, traditional silicon FETs are reaching the scaling limits, and it is therefore urgent to explore alternative paradigms. Two-dimensional (2D) materials attract great research enthusiasm, owing to their abilities to suppress short-channel effects. Herein, we evaluate the electronic properties and device performance of ultrascaled 2D ${\mathrm{Sn}\mathrm{S}}_{2}$ metal-oxide-semiconductor FETs (MOSFETs) via ab initio simulations. Specifically, the ${I}_{\mathrm{on}}$ value of the 5.5 nm monolayer ${\mathrm{Sn}\mathrm{S}}_{2}$ n-MOSFETs is ultrahigh, up to 3400 \textmu{}A/\textmu{}m, as a result of the small effective masses of the conduction-band minimum of monolayer ${\mathrm{Sn}\mathrm{S}}_{2}$. Until the channel length is scaled down to 4 nm, the MOSFETs can fulfill the standards of ${I}_{\mathrm{on}}$, delay time, and power dissipation product of the International Roadmap for Devices and Systems (IRDS) 2018 goals for high-performance devices. Moreover, the 5.5 nm monolayer ${\mathrm{Sn}\mathrm{S}}_{2}$ n-MOSFETs can also fulfill the IRDS 2018 requirements for the 2028 horizon for low-power applications. This work demonstrates that monolayer ${\mathrm{Sn}\mathrm{S}}_{2}$ is a favorable channel material for future competitive ultrascaled devices.