Controlling Threshold Voltage of CMOS SOI Nanowire FETs With Sub-1 nm Dipole Layers Formed by Atomic Layer Deposition
Dongqi Zheng, Wonil Chung, Zhizhong Chen, Mengwei Si, Calista Wilk, Peide D. Ye
Abstract
In this article, bidirectional control of threshold voltage (<inline-formula> <tex-math notation="LaTeX">${V}_{T}$ </tex-math></inline-formula>) is realized in both n- and p-silicon-on-insulator (SOI) nanowire FETs (NWFETs) by using sub-1 nm atomic-layer-deposited (ALD) dipole layers (Y<sub>2</sub>O<sub>3</sub> and Al<sub>2</sub>O<sub>3</sub>) for the first time. A 0.7 nm Y<sub>2</sub>O<sub>3</sub> inserted between bottom native SiO<sub><i>x</i></sub> (< 1 nm) and top HfO<sub>2</sub> (3 nm) can shift the <inline-formula> <tex-math notation="LaTeX">${V}_{\text {TH}}$ </tex-math></inline-formula> by −138 and −58 mV for n- and p-NWFET, respectively, while 0.7 nm Al<sub>2</sub>O<sub>3</sub> can shift the <inline-formula> <tex-math notation="LaTeX">${V}_{T}$ </tex-math></inline-formula> of n-NWFET by +219 mV and p-NWFET by +134 mV. The tunability of such a high<i>-k</i> superstructure for the flat band voltage (<inline-formula> <tex-math notation="LaTeX">${V}_{\text {FB}}$ </tex-math></inline-formula>) shift of capacitors and <inline-formula> <tex-math notation="LaTeX">${V}_{\text {TH}}$ </tex-math></inline-formula> shift of planar n-SOI FETs are also investigated. Furthermore, to concisely control the <inline-formula> <tex-math notation="LaTeX">${V}_{\text {TH}}$ </tex-math></inline-formula> and <inline-formula> <tex-math notation="LaTeX">${V}_{\text {FB}}$ </tex-math></inline-formula> as design, capacitors fabricated with quadra-layer (SiO<sub><i>x</i></sub>/HfO<sub>2</sub>/Al<sub>2</sub>O<sub>3</sub>/Y<sub>2</sub>O<sub>3</sub>) high<i>-k</i> superstructure were fabricated and 3 mV <inline-formula> <tex-math notation="LaTeX">${V}_{\text {FB}}$ </tex-math></inline-formula> shift is achieved by carefully adjusting the composition of intermixed-dipole layers. This work points out the route to concisely tune the threshold voltage of complementary metal-oxide-semiconductor (CMOS) FETs with the desired direction and strength.