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Nanosheet-based Complementary Field-Effect Transistors (CFETs) at 48nm Gate Pitch, and Middle Dielectric Isolation to enable CFET Inner Spacer Formation and Multi-Vt Patterning

Hans Mertens, Maryam Hosseini, T. Chiarella, D. L. Zhou, S. Wang, G. Mannaert, Emmanuel Dupuy, D. Radisic, Z. Tao, Yusuke Oniki, Andriy Hikavyy, R. Rosseel, A. Mingardi, S. Choudhury, P. Puttarame Gowda, Farid Sebaai, A. Peter, K. Vandersmissen, Jean-Philippe Soulié, A. De Keersgieter, Lucas Petersen Barbosa Lima, C. Cavalcante, Dmitry Batuk, Gerardo Martínez, J. Geypen, F. C. Seidel, Kris Paulussen, Paola Favia, Juergen Boemmels, Roger Loo, Patrick Wong, A. Sepulveda Marquez, Boon Teik Chan, Jérôme Mitard, S. Subramanian, S. Demuynck, E. Dentoni Litta, Naoto Horiguchi, Srikanth Samavedam, S. Biesemans

202354 citationsDOI

Abstract

We report on Si nanosheet monolithic Complementary Field-Effect Transistors (CFETs) at industry-relevant 48nm gate pitch, with source-drains (SDs) and SD contacts formed for either bottom or top devices. SD epi patterning at 30nm vertical N-P space and high-aspect-ratio SD contact formation are successfully demonstrated. Functional devices with excellent subthreshold slope $(SS_{SAT}=7075$ mV/dec) are reported for bottom and top devices, for both N- and PMOS. Middle dielectric isolation (MDI) formed by SiGe replacement processing is introduced as an enabler for monolithic CFET inner spacer formation and multi-Vt patterning.

Topics & Concepts

PMOS logicNanosheetMaterials scienceDielectricTransistorOptoelectronicsSubthreshold slopeGate dielectricField-effect transistorSubthreshold conductionNanotechnologyElectrical engineeringVoltageEngineeringSemiconductor materials and devicesAdvancements in Semiconductor Devices and Circuit DesignIntegrated Circuits and Semiconductor Failure Analysis
Nanosheet-based Complementary Field-Effect Transistors (CFETs) at 48nm Gate Pitch, and Middle Dielectric Isolation to enable CFET Inner Spacer Formation and Multi-Vt Patterning | Litcius