Design and Deep Insights into Sub-10 nm Spacer Engineered Junctionless FinFET for Nanoscale Applications
V. Bharath Sreenivasulu, Narendar Vadthiya
Abstract
In this paper, we have studied the impact of various dielectric single- k (S- k ) and dual- k (D- k ) spacers on optimized Junctionless (JL) FinFET at nano-regime by using hetero-dielectric oxide based (Hf x Ti 1−x O 2 ) gate stack to enhance the sub-threshold performance of the device. Performance impact of outer low- k spacer variation on D- k spacer by fixing inner high- k spacer has been reported. In this move, it is noticed that the I ON / I OFF ratio shifted from 8.70 × 10 5 to 1.30 × 10 6 which is about ∼1.5x times improvement. Along with DC characteristics, analog/RF and linearity metrics are extracted and analysed. Due to a better gate electrostatic integrity (EI) at an extremely scaled <mml:math xmlns:mml="http://www.w3.org/1998/Math/MathML" overflow="scroll"> <mml:msub> <mml:mrow> <mml:mi>L</mml:mi> </mml:mrow> <mml:mrow> <mml:mi>G</mml:mi> </mml:mrow> </mml:msub> <mml:mo>,</mml:mo> </mml:math> an optimally designed D- k spacer reveals a better DC and analog performance characteristics. The S- k spacer reveals a better performer in power consumption, dynamic power, RF, and linearity characteristics at nano scale. Furthermore, the scaling possibilities by spacers on DC and Analog performance at <mml:math xmlns:mml="http://www.w3.org/1998/Math/MathML" overflow="scroll"> <mml:msub> <mml:mrow> <mml:mi>L</mml:mi> </mml:mrow> <mml:mrow> <mml:mi>G</mml:mi> </mml:mrow> </mml:msub> </mml:math> = 10 nm FinFET with tri-gate geometry at <mml:math xmlns:mml="http://www.w3.org/1998/Math/MathML" overflow="scroll"> <mml:msub> <mml:mrow> <mml:mi>L</mml:mi> </mml:mrow> <mml:mrow> <mml:mi>G</mml:mi> </mml:mrow> </mml:msub> </mml:math> of 7 nm, 5 nm, and 3 nm are also examined. It has been noticed that the enhanced performance with the tri-gate structure is best suitable for future technological nodes.