Monolithic-CFET with Direct Backside Contact to Source/Drain and Backside Dielectric Isolation
A. Vandooren, Karen Stiers, Chuanxiang Sheng, C. Cavalcante, Motaharesadat Hosseini, Dmitry Batuk, An Peng, X. Zhou, Hans Mertens, A. Veloso, A. Mingardi, S. Kumar, Rajendra K. Saroj, Koen D’havé, T. Chiarella, J. Bömmels, Roger Loo, Erik Rosseel, Clément Porret, Yosuke Shimura, Aparna Akula, S. Choudhury, Vincent Brissonneau, Emmanuel Dupuy, Tanmoy Sarkar, A. Peter, N. Jourdan, Jean-Philippe Soulié, K. Vandersmissen, Serena Iacovo, D. Montero, Evi Vrancken, Farid Sebaai, P. Puttarame Gowda, K. Lai, Nunzio Buccheri, P. Matagne, Boon Teik Chan, A. Sepulveda Marquez, R. Langer, I. Gyo Koo, Efrain Altamirano Sánchez, K. Devriendt, Frédéric Lazzarino, Jérôme Mitard, J. Geypen, Eva Grieten, Y-F. Chen, F. Verbeek, H. Pollenus, J. Heijlen, Lucas Petersen Barbosa Lima, Frank Holsteyns, S. Subramanian, Naoto Horiguchi, S. Demuynck, S. Biesemans
Abstract
This work reports on demonstration of monolithic complementary field effect (CFET) transistors using direct backside (BS) contact (DBC) to source and drain (SD) of the bottom PMOS device. We compare two integration options to avoid shorts between DBC and gate and/or Si substrate relying either on the use of an offset spacer or on the formation of a bottom dielectric isolation from the backside (BS-BDI). We show that a DBC layer registration accuracy of < 3 nm can be achieved with high order correction modelling which can be transferred to consecutively processed BS layers. Both integration options result in functional bottom (pFET) and top (nFET) CMOS devices on a common gate at 60 nm gate pitch. While the BS-BDI option requires additional process steps, it results into parasitic transistor leakage suppression due to replacement of the Si substrate under the gate by dielectric. Moreover, it provides better tolerance to DBC misplacement and enables maximizing contacting area.