Gate Oxide Degradation Condition Monitoring Technique for High-Frequency Applications of Silicon Carbide Power MOSFETs
Javad Naghibi, Sadegh Mohsenzade, Kamyar Mehran, Martin P. Foster
Abstract
Gate oxide degradation, which considerably affects turn- <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</small> /- <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">off</small> dynamics of the switch, embraces a large percentage of chip-related failure modes both in silicon and silicon carbide power MOSFETs. The gate oxide layer is thinner in silicon carbide power MOSFETs in comparison to their silicon-based counterparts. Consequently, the problem of gate oxide degradation has become a more crucial impediment in achieving reliable performance in silicon carbide power MOSFETs. This problem is even more severe in high-frequency applications due to higher EMI signature and complicated and costly measurement. In this article, a reliable fully analog cost-effective gate oxide degradation condition monitoring technique is proposed and validated. High-order harmonics magnitudes of drain–source voltage are used to produce a dc signal as the aging precursor of the gate oxide region. Using a dedicated degradation setup, the credibility of the developed condition monitoring technique was examined at different rates of gate oxide degradation for 650-V/22-A silicon carbide discrete MOSFET. In 200-kHz, 217-V switch operation, the proposed precursor showed 68% change in comparison to its initial value. This brings a high-resolution assessment on the reliability level of the switch gate oxide region.