Establishing Thermal Air-cooled Limit for High Performance Electronics Devices
Gamal Refai-Ahmed, Hoa Do, Yaser Hadad, Srikanth Rangarajan, Bahgat Sammakia, Vadim Gektin, Tahir Cader
Abstract
This manuscript explores the design and optimization of an air-cooled heat sink and establishes thermal performance limits for the air-cooling of high power electronic devices. The air-cooling limit is established based on a numerical model. This model correlates the thermal performance of an FPGA with the test data from a standalone active VCK5000 PCIe card. Using Ansys Icepak V19.1 software, a series of CFD (computational fluid dynamics) simulations is performed with an FPGA power level of 1,000W, which is recently discussed in different roadmap such as HIR [1]. The purpose of the CFD model is to determine the temperature and flow fields over a range of airflow rates, and to develop a correlation for the convective thermal resistance, as a function of the flow parameters. A heat sink shape optimization is performed by simple Brute force in order to minimize the pressure drop and die maximum case temperature. The effects of the heat sink's fin thickness and channel spacing are analyzed numerically. The optimization is performed for the constant values of air velocity and chip power. The optimized air-cooled heat sink with a vapor chamber base using a thermal interface material (TIM) with an effective thermal conductivity of 20W/mK and effective thickness of 70um is shown to able to operate at a heat flux 45-55W/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> for either 1U or 4U server, while still meeting max allowable FPGA operating case temperature.