A Hardware-Efficient Approximate Multiplier Combining Inexact Same-weight N:2 Compressors and Remapping Logic with Error Recovery
Renrui Duan, Mingtao Zhang, Yi Guo, Shinichi Nishizawa, Shinji Kimura
Abstract
Approximate computing can trade accuracy for smaller power, delay, and area. So, approximate computing is hardware-efficient for fault-tolerant applications which do not require full precision, such as image processing and machine learning. This paper proposes same-weight N:2 compressors based on the probability analysis, and construct approximate multipliers combining proposed N:2 compressors, remapping logic and constant-truncation with its error recovery circuit. Evaluation results using commercial 65 nm process library show that proposed 8×8 multiplier has good hardware-accuracy trade-off. It reduces the power by 39%, the delay by 17%, the area by 34% and the power-delay-area-product (PDAP) by 67% with an MRED of 1.27% when compared to the exact multiplier. The proposed methods show the better PDAP compared with other approximate multipliers with almost the same MRED.