Motor-Imagery EEGNet-Based Processing on a Low-Spec SoC Hardware
Ana Caren Hernández-Ruiz, Daniel Enériz, N. Medrano, B. Calvo
Abstract
One of the most popular Brain-Computer Interface (BCI) paradigms is the classification of motor imagery tasks using Electroencephalograph signals (EEG). Recent works suggest the use of Convolutional Neural Networks (CNNs) to both extract the EEG features and classify them in a single compact solution. Since BCIs are meant to be run in embedded hardware, compact models and data reduction strategies are necessary. An EEGNet-based model is presented in this work, which achieves results similar to those of the state-of-the-art of 83.15 %, 75.74 % and 65.75 % in classification accuracy on 2-, 3-, and 4-class MI tasks in global validation on the Physionet Motor Movement/Imagery dataset. Taking advantage of its lower model complexity, a preliminary FPGA processor design using fixed-point datatypes is introduced, to evaluate resources consumption and latency on a low-spec system on chip approach.