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Ultralow Power E-Band Low-Noise Amplifier With Three-Stacked Current-Sharing Amplification Stages in 28-nm CMOS

Liang Qiu, Jiabing Liu, Qianyi Dong, Zhihao Lv, Kailong Zhao, Shengjie Wang, Yen‐Cheng Kuan, Qun Jane Gu, Xiaopeng Yu, Chunyi Song, Zhiwei Xu

2022IEEE Microwave and Wireless Components Letters16 citationsDOI

Abstract

This letter presents a differential ultralow power low-noise amplifier (LNA) with stacked three-stage common-source (CS) amplification cells. A three-coil transformer is developed to boost each stage’s <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$g_{m}$ </tex-math></inline-formula> and reuse current, which renders high gain, low noise, and low power consumption. The proposed LNA has been implemented in a 28-nm CMOS process and achieves a peak gain of 13.48 dB and a minimum noise figure (NF <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$_{\mathrm {min}}$ </tex-math></inline-formula> ) of 4.56 dB. The measured 3-dB gain bandwidth ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${\text {BW}}_{3\,\text {dB}}$ </tex-math></inline-formula> ) is from 69.6 to 76.2 GHz. The LNA consumes 3.64-mW power from a 1.4-V supply and occupies 0.088-mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> area excluding pads.

Topics & Concepts

AmplifierCMOSElectrical engineeringPhysicsMathematicsTopology (electrical circuits)Electronic engineeringComputer scienceAlgorithmEngineeringRadio Frequency Integrated Circuit DesignAdvanced Power Amplifier DesignAnalog and Mixed-Signal Circuit Design
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