Design of Non-volatile Capacitive Crossbar Array for In-Memory Computing
Yuan-Chun Luo, Anni Lu, Jae Hur, Shaolan Li, Shimeng Yu
Abstract
Capacitive crossbar array with non-volatile ferroelectric capacitors as synaptic devices is designed and analyzed. We developed Hf <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</sub> Zr <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1-x</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> (HZO) based ferroelectric capacitors that exhibit tunable and non-volatile small-signal capacitance states. We claim that the capacitive crossbar architecture can perform read-disturbance-free and energy-efficient in-memory computing. In this paper, we first show the device characteristics and discuss the underlying physical mechanism. Moving to the array analysis, we identify the optimal ratio between reference capacitors (C <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ref</sub> ) and ferroelectric capacitors (CFE) to maximize the output voltage swing >50 mV. Then we explore the tradeoff between delay and output switching and aim for delay <; 30ns. Based on the extracted experimental data from HZO capacitor and the array-level SPICE simulation, we show that a 128×128 non-volatile capacitive crossbar array is compatible with 3-bit analog-to-digital converter (ADC) for partial sum quantization even under thermal noise. The optimized capacitive crossbar design can achieve 3.8 pJ per vector-matrix multiplication, which is 14.3×~57.3× lower energy consumption compared to the representative resistive crossbar array.