Fully Parallel, Flexible, and Conflict-Free Interleaver Design using Processing in Memory

Abstract

This paper presents a fully parallel and flexible realization of interleavers and de-interleavers, which are required to design high-throughput channel decoders/encoders for the baseband processors. The key idea is to represent the interleaving pattern as a permutation matrix, and then employ the concept of processing in memory to realize the interleaver by an array of memristors. This scheme enables us to implement both interleaver and de-interleaver using the same hardware.

Topics & Concepts