Demonstration of Vertically-stacked CVD Monolayer Channels: MoS<sub>2</sub> Nanosheets GAA-FET with I<sub>on</sub>>700 µA/µm and MoS2/WSe2 CFET
Xiong Xiong, Anyu Tong, Xin Wang, Shiyuan Liu, Xuefei Li, Ru Huang, Yanqing Wu
Abstract
Vertical stacking of atomic layer thin channel has been challenging due to the top-gate dielectric integration and complicated process, which typically yield in deteriorated performance. In this work, we demonstrate the 2-monolayer-MoSc-stacked nanosheets with a sequentially layer-by-layer fabrication process using a gate-a11-around fashion. Compared with the 1-channel back-gate transistor, the 2-channel stacked nanosheets (SN) transistor exhibits more than twice of gm improvement. The high I <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</inf> >400 µA/µm per channel footprint at V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">d</inf> = 1 V is achieved due to short gate length of 100 nm, and low contact resistance of 0.77 k Ω*µm. Statistics of hundreds of devices with various channel lengths show the performance evolution trend and monolithic integration potential based on the large-scale CVD -grown 2D materials. Furthermore, the vertical-stacked MoS <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> /WSe <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> complementary FETs (CFETs) based on CVD grown are also demonstrated for the first time with about 50% footprint reduction, as compared to the planar devices.