Energy Efficient Memristor-Based Subtractors and Comparator for In-Memory Computing in MAGIC
Nandit Kaushik, B. Srinivasu
Abstract
Applications involving large datasets incur substantial energy costs due to frequent data transfers between memory and processing units. Utilizing memristors within a memristive crossbar to execute logic operations is a characteristic of In-Memory-Computing (IMC), resulting in improved processing speed and energy efficiency. This paper proposes MAGIC-based IMC-capable memristive subtractors optimized for area, speed, and energy consumption. The proposed high-speed MAGIC serial design is 33% faster than the current IMPLY-based serial subtractor by computing the 32-bit subtractor output in 449 steps and 294 steps through the proposed MAGIC parallel design. Next, we use the proposed subtractor designs to create a comparator and implement max pooling operations. A n-bit comparator, designed through the proposed subtractor, performs the comparison in 9n+3 steps. Further, a n-bit max pooling operation for a 2×2 feature map takes 28n+2 steps. Regarding energy consumption, the MAGIC design exhibits superior performance compared to other designs, demonstrating an average savings of 93% to 95% in comparison to the IMPLY-based subtractor and comparator designs. All the designs are functionally verified through simulations using the VTEAM model, and energy is calculated from these simulations.