Forksheet FETs for Advanced CMOS Scaling: Forksheet-Nanosheet Co-Integration and Dual Work Function Metal Gates at 17nm N-P Space
Hans Mertens, R. Ritzenthaler, Yusuke Oniki, B. Briggs, Boon Teik Chan, Andriy Hikavyy, T. Hopf, G. Mannaert, Zheng Tao, Farid Sebaai, A. Peter, K. Vandersmissen, Emmanuel Dupuy, Erik Rosseel, Dmitry Batuk, J. Geypen, Gerardo Martínez, D. Abigail, Eva Grieten, K. Dehave, Jérôme Mitard, S. Subramanian, L.-Å. Ragnarsson, Pieter Weckx, Doyoung Jang, Bilal Chehab, Geert Hellings, Julien Ryckaert, E. Dentoni Litta, Naoto Horiguchi
Abstract
We report on forksheet N- and PFETs co-integrated with gate-all-around nanosheet FETs. The forksheet short-channel control is on par with nanosheets down to 22nm gate length (SS SAT =66-68mV/dec). Forksheet I ON and I OFF characteristics are improved by post-channel-release wet clean optimization, attributed to gate stack interface trap density reduction. Dual work function metal gates are integrated at 17nm N-P space, highlighting a key benefit of forksheets for CMOS area scaling.