13.5 A 64Gb/s/pin PAM4 Single-Ended Transmitter with a Merged Pre-Emphasis Capacitive-Peaking Crosstalk-Cancellation Scheme for Memory Interfaces in 28nm CMOS
WU Weitao, Hongzhi Wu, Liping Zhong, Xuxu Cheng, Xiongshi Luo, Dongfan Xu, Catherine Wang, Zhenghao Li, Quan Pan
Abstract
With the development of massive computing and AI technologies, the memory interface is critical to achieve higher computational throughput. Increasing the parallel-channel density is an effective solution to improve the throughput [1]. However, due to a reduced channel pitch, the crosstalk between adjacent lanes becomes severe and degrades signal integrity. Advanced DRAM applications, such as GDDR6x [2], have adopted PAM-4 signaling to increase transmission speed; unfortunately, PAM-4 is more sensitive to crosstalk. Various TX crosstalk cancellation (XTC) techniques have been reported [3] –[5], but these techniques mainly focus on NRZ. The de-emphasis FIR-based XTC (FIR-XTC) in [3] increases static power consumption and reduces the TX-output SNR. Phase predistortion is utilized in [4] to eliminate crosstalk; however, this method has limited elimination capacity and high-power consumption. Fibonacci coding used in [5] decreases the pin efficiency by 25% and consumes substantial power for PAM-4, due to the increased coding complexity. Therefore, an efficient PAM-4 crosstalk cancellation technique that does not sacrifice pin efficiency and the TX-output SNR is highly desired.