Performance improvement of spacer engineered n-type SOI FinFET at 3-nm gate length
V. Bharath Sreenivasulu, Narendar Vadthiya
Topics & Concepts
Materials scienceSilicon on insulatorOptoelectronicsIonDielectricDrain-induced barrier loweringScalingSubthreshold conductionSubthreshold slopeSiliconTransistorMOSFETNanotechnologyElectrical engineeringThreshold voltageVoltageChemistryMathematicsGeometryOrganic chemistryEngineeringSemiconductor materials and devicesAdvancements in Semiconductor Devices and Circuit DesignFerroelectric and Negative Capacitance Devices