Specific On-Resistance Reduction for the LDMOS Using Separated Composite Dielectric Trenches
Jiafei Yao, Tianci Xu, Mingshun Sun, Xin Liu, Kemeng Yang, Man Li, Jing Chen, Maolin Zhang, Jun Zhang, Yufeng Guo
Abstract
In this article, a novel lateral double-diffused metal oxide semiconductor (LDMOS) with separated composite dielectric trenches (SCDT LDMOS) is proposed. The main features of SCDT LDMOS are that the depths of gate trench and lateral separated trenches in the drift region are the same, and the high- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${k}$ </tex-math></inline-formula> dielectric is deposited into each trench in one process. The gate trench is filled with high- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${k}$ </tex-math></inline-formula> gate dielectric and metal, which forms the vertical high- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${k}$ </tex-math></inline-formula> metal gate (HKMG) structure, and the lateral separated trenches filled with high- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${k}$ </tex-math></inline-formula> dielectric and SiO2 form the composite dielectric trenches. The composite dielectric trenches assist in the depletion of the drift region, which improves the drift doping concentration and reduces the specific ON-resistance ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${R} _{{ \text {on,sp}}}$ </tex-math></inline-formula> ). Meanwhile, the vertical HKMG structure effectively reduces <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${R} _{{ \text {on,sp}}}$ </tex-math></inline-formula> and threshold voltage ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V} _{\text {TH}}$ </tex-math></inline-formula> ). The simulation results show that the SCDT LDMOS with the HK dielectric thickness of 300 nm and the permittivity of 250 has reduced <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${R} _{{ \text {on,sp}}}$ </tex-math></inline-formula> by 45.7%, increased the figure of merit (FOM) by 83.5%, and reduced <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V} _{\text {TH}}$ </tex-math></inline-formula> from 2 to 0.83 V when compared with the conventional LDMOS. The feasible process is designed and simulated, and the key experiment of the HK deposition process is carried out to verify the feasibility of the SCDT LDMOS.