Switched-capacitor multi-level inverter with equal distribution of the capacitors discharging phases
Zhiyuan Xu, Xiaofeng Zheng, Tong Lin, Jia Yao, Adrian Ioinovici
Abstract
A new switched-capacitor (2n+1) levels inverter with a single input source and equal charge of the capacitors at the input voltage V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">in</sub> is presented. Compared with its peers from the same class of inverters, the proposed one features an equal or lower components count referred to the boost factor. And, it presents an additional advantage: each voltage level can be obtained by using different capacitors in the discharging phase, such that the decreasing part of the staircase output waveform can be synthesized with different switching topologies than those used in the increasing part. As a consequence, all the capacitors are discharged at the same voltage value at the end of each half-cycle, allowing for the use of smaller capacitors of equal values. When the capacitors are connected in parallel in the charging phase, there is no need to equalize their voltages, so no additional current spikes appear. This also implies less electromagnetic emission (EMI). Two types of modulation strategies are proposed. A half-height fundamental switching frequency modulation strategy allows for reaching the desired peak of the output voltage during the highest voltage level operation. It is advantageous in application of the inverter as a front end of a grid supplied by green sources of energy. A high frequency (f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">s</sub> =200 kHz) modulation strategy accompanied by a duty-cycle control is advantageous for applications which require miniaturization. A 9-level switched-capacitor multi-level inverter (SCMLI) is analyzed and designed. The power losses are calculated. The experimental results for a 9-level inverter with V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">in</sub> =40 V, V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">out</sub> =110 Vrms 50 Hz, 200 W confirm the theoretical expectations.