Double-Node-Upset Self-Recoverable Latch Design for Wide Voltage Range Application
Yuxin Bai, Xin Chen, Xinjie Zhou, Yanan Yin, Ying Zhang
Abstract
This brief presents a double node upset (DNU) self-recoverable latch (DRLW) for wide voltage range through a clock-gated recovery array and a short critical path. Implemented in a 28nm CMOS process, DRLW latch provides <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$0.83\times $ </tex-math></inline-formula> , <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$2.34\times $ </tex-math></inline-formula> and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$5.25\times $ </tex-math></inline-formula> average reductions in power, delay and delay-power-area product (DPAP) among all considered latches at 0.9V/1GHz, respectively. At the worst-case, DRLW latch is able to operate steadily at 0.25V/250KHz and always keeps the highest operating frequency and lowest power consumption compared with the considered latches in near-threshold voltage (NTV) region. Moreover, both at the extreme process, voltage, temperature (PVT) conditions and NTV region, DRLW latch can achieve DNU self-recovery for all internal and output nodes.