Engineering Surface Texture of Pads for Improving CMP Performance of Sub-10 nm Nodes
Aniruddh J. Khanna, Veera Raghava Kakireddy, Jason Fung, Mayu Yamamura, Puneet Jawali, Ashwin Chockalingam, Nandan Baradanahalli Kenchappa, Daniel Redfield, Rajeev Bajaj
Abstract
Shallow trench isolation (STI) chemical mechanical planarization (CMP) will continue to be a critical step in the device fabrication of future technology nodes. A CMP process needs the right combination of pad, slurry, and pad conditioner to be able to deliver the best performance. Engineered pad surface along with usage of non-Prestonian ceria slurries can be used to solve key STI CMP challenges. Herein, it is demonstrated that relative to a reference pad, reducing and optimizing pad surface roughness, can help improve material removal rate by 26%–95% at different wafer pressures, lower the dishing by 34%–51% for feature size of 50–200 μ m, thereby leading to an improved planarization performance. This work illustrates that the surface texture of a pad can be used to achieve a stable dishing range over different feature scales for various over polish times. Also, optimizing the pad surface roughness minimizes slurry consumption by 33% and enables polishing at a lower downforce. Further, it is demonstrated that relative to a reference pad, defectivity can be improved up to 85% for the pad without impacting the planarization performance by reducing the pad material hardness and polishing at an optimized pad surface roughness.