Highly Selective SiGe Dry Etch Process for the Enablement of Stacked Nanosheet Gate-All-Around Transistors
Curtis Durfee, Subhadeep Kal, S. Pancharatnam, Maruf Bhuiyan, Ivo Otto, Matthew Flaugh, Jeffrey S. Smith, D. Chanemougame, Cheryl Alix, Huimei Zhou, Julien Frougier, Andrew Greene, Michael Belyansky, Kôji Watanabe, Jingyun Zhang, Daniel Schmidt, Mary Breton, Kai Zhao, Miaomiao Wang, Veeraraghavan Basker, Aelan Mosden, Nicolas Loubet, Dechao Guo, Peter Biolsi, Bala Haran, Huiming Bu
Abstract
Horizontally stacked nanosheet gate-all-around devices enable area scaling of transistor technology, while providing improved electrostatic control over FinFETs for a wide range of channel widths within a single chip for simultaneous low power applications and high-performance computing. Fabrication of inner spacers and Si channels is challenging, but essential to device performance, yield, and reliability. We elucidate these challenges and detail their impact to the device. We overcome these challenges with novel, highly selective, isotropic SiGe dry etch techniques which enable precise, robust inner spacer and channel formation. Finally, we demonstrate substantial improvements to relevant device parameters: resistance, drive current, transconductance, threshold voltage, breakdown voltage, bias temperature instability and overall variability.