Middle Interlayer Engineered Ferroelectric NAND Flash Overcoming Reliability and Stability Bottlenecks for Next‐Generation High‐Density Storage Systems
Giuk Kim, Sang Ho Lee, Hyojun Choi, Yangjin Jung, W.-S. Kim, Sanghyun Park, Kwangyou Seo, Kwangsoo Kim, Wanki Kim, Daewon Ha, Mincheol Shin, Jinho Ahn, Sanghun Jeon
Abstract
Abstract Multilevel storage and low‐voltage operation position ferroelectric transistors as promising candidates for next‐generation nonvolatile memory. Among them, gate‐injection‐type ferroelectric transistors offer improved vertical scalability and power efficiency for three‐dimensional (3D) NAND flash. However, their intricate interplay between polarization switching and charge trapping complicates systematic understanding of degradation mechanisms, limiting strategies to improve reliability and stability. Here, gate stack engineering incorporating middle interlayers within HfZrO x matrix is presented to modulate polarization dynamics, strengthening the coupling of dual mechanisms and overcoming long‐standing reliability and stability bottlenecks in ferroelectric NAND operation. This approach achieves a memory window up to 11 V, an operating voltage below 18 V, triple‐level‐cell retention beyond 10 years, disturbance immunity, and 54% reduced threshold voltage variability. A 20% reduction in program voltage compared to conventional NAND enables aggressive vertical scaling, leading to 25% higher bit‐density. Furthermore, analytical modeling provides insights into gate stack optimization. These findings establish ferroelectric NAND as a scalable, energy‐efficient solution for next‐generation storage.