3D AND: A 3D Stackable Flash Memory Architecture to Realize High-Density and Fast-Read 3D NOR Flash and Storage-Class Memory
Hang-Ting Lue, Guan-Ru Lee, Teng-Hao Yeh, Tzu‐Hsuan Hsu, Chieh Roger Lo, Cheng-Lin Sung, Wei-Chen Chen, Chia-Tze Huang, Kuan-Yuan Shen, Meng-Yen Wu, Pishan Tseng, Min-Feng Hung, Chia-Jung Chiu, Kuang-Yeu Hsieh, Keh-Chung Wang, Chih‐Yuan Lu
Abstract
We demonstrate a 3D stackable AND-type Flash memory architecture for high-density and fast-read non-volatile memory solution. The device is based on a gate-all-around (GAA) macaroni thin-body device, with two vertical buried diffusion lines by N <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> doped poly plug to connect all memory cells in a parallel way to achieve 3D AND-type array. High sensing current >6uA enables fast Tread ~100ns like NOR Flash, while the structure can enable hundreds of stacked layers eventually. Large transistor ON/OFF ratio of >5 orders, >5V Vt memory window, 100K Endurance, read-disturb free property, and small RTN are demonstrated in our 3D architecture using the BE-MANOS charge-trapping device. This architecture is promising to realize high-density 3D NOR Flash and future storage-class memory (SCM).