Characterization of Early Breakdown of SiC MOSFET Gate Oxide by Voltage Ramp Tests
Yongju Zheng, Rahul Potera, Tony Witt
Abstract
In this work, we studied the behavior of gate oxide (GOx) breakdown of 1200V 4H-SiC DMOSFETs by a screening process of voltage ramp (vramp). By employing vramp between 40-50V on a 50nm GOx, early failures below 50V, which could be infant or extrinsic failures in time-dependent-dielectric-breakdown (TDDB) testing, were screened out. In addition, the results indicate that early failures correlate to the density of large pit defects on epi-wafer as well as to gate area of the devices, which have implications on the epi quality required for MOSFETs and for achievable yield on large-area SiC MOSFETs screened for long-term gate reliability. We also identified an electric field limit on the screening voltage, above which the traditional upward drift of threshold voltage (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Th</sub> ) due to positive gate bias transitions to a downward drift, which can seriously degrade device performance.