Novel Vertical Channel-All-Around (CAA) In-Ga-Zn-O FET for 2T0C-DRAM With High Density Beyond 4F<sup>2</sup> by Monolithic Stacking
Xinlv Duan, Shijie Huang, Junxiao Feng, Jiebin Niu, Haibo Qin, Shihui Yin, Guangfan Jiao, Daniele Leonelli, Xiaoxuan Zhao, Zhaogui Wang, Weiliang Jing, Zhengbo Wang, Ying Wu, Jeffrey Xu, Qian Chen, Xichen Chuai, Congyan Lu, Wenwu Wang, Guanhua Yang, Di Geng, Ling Li, Ming Liu
Abstract
For the first time, we propose a stackable vertical channel-all-around (CAA) In–Ga–Zn-O field-effect transistor (IGZO FET) for high-density 4F<sup>2</sup> and long-retention 2T0C dynamic random access memory (DRAM) application. The device is fabricated in a back-end-of-line (BEOL) compatible process flow where the channel and gate-stack are deposited by plasma-enhanced atomic layer deposition (PEALD). The impact of IGZO cycle ratio and plasma power on the device’s electrical performance is studied. An optimized 50-nm channel-length CAA IGZO FET achieved <inline-formula> <tex-math notation="LaTeX">${I}_{ \mathrm{\scriptscriptstyle ON}} > 30 ~\mu \text{A}/\mu \text{m}$ </tex-math></inline-formula> and <inline-formula> <tex-math notation="LaTeX">${I}_{ \mathrm{\scriptscriptstyle OFF}}$ </tex-math></inline-formula> below <inline-formula> <tex-math notation="LaTeX">$1.8\times10$ </tex-math></inline-formula><sup>−17</sup> <inline-formula> <tex-math notation="LaTeX">$\mu \text{A}/\mu \text{m}$ </tex-math></inline-formula> at <inline-formula> <tex-math notation="LaTeX">${V}_{\text {DS}} = 1$ </tex-math></inline-formula> V. A long retention of 300 s has been experimentally verified for the CAA IGZO 2T0C bit cell, making it a potential candidate for low-power 2T0C DRAM with ultralow refresh frequency. Finally, by monolithically stacking the vertical CAA IGZO FETs with 130-nm critical dimension (CD) to form 2T0C bit cells, we demonstrate the feasibility of the proposed BEOL-compatible 2T0C DRAM for further density scaling beyond 4F<sup>2</sup>.