High-Performance Floating Gate Heterostructure With WSe<sub>2</sub>-MoS<sub>2</sub> Diode Channel for Neural Synapse
Zi-Jia Su, Hengxiao Cheng, Xiyu Sun, Haiding Sun, Chengjie Zuo
Abstract
In this letter, we propose a novel floating gate heterostructure based on two-dimensional (2D) materials, with WSe <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> -MoS <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> forming a p-n diode to serve as the channel and multilayer graphene as the floating gate. Different from previous floating gate devices, the p-n diode is used here instead of a single layer of 2D material in the channel layer to improve the gate-tuning capability. Our device exhibits a large memory window (14 V), high ON/OFF ratio ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$10^{{4}}$ </tex-math></inline-formula> ), stable retention (5000 s), and cyclic endurance (1500 cycles). When used as a neural synapse, the device is able to realize a high max-min conductance ratio ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${G} _{\text {max}}/{G} _{\text {min}}$ </tex-math></inline-formula> = 28), low nonlinearity coefficients ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\nu $ </tex-math></inline-formula> ) of −2.0 for potentiation and −2.5 for depression, and record low energy consumption of 9 (15) aJ per spike in potentiation (depression). Our work provides a novel design of 2D-material heterostructure to be used as an implementation of neural synapses for neuromorphic computing.