Deep Sub-Micron Self-Aligned Bottom-Gate Amorphous InGaZnO Thin-Film Transistors With Low-Resistance Source/Drain
Yuhan Zhang, Jiye Li, Yuqing Zhang, Huan Yang, Yuhang Guan, Mansun Chan, Lei Lü, Shengdong Zhang
Abstract
A deep sub-micron self-aligned bottom-gate (SABG) amorphous InGaZnO (a-IGZO) thin-film transistor (TFT) technology was developed. The implementation of a backside exposure technique enables the realization of a self-aligned structure, while an argon (Ar) plasma treatment minimizes the source/drain resistance ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${R} _{\text {SD}}$ </tex-math></inline-formula> ). High-performance metrics were well maintained on the fabricated SABG a-IGZO TFT with a channel length of 302 nm (effective channel length of 208 nm), including a low off-state current around 10−14 A/ <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> , a subthreshold swing of 103.8 mV/dec, a decent mobility of 7.48 cm2/ <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text {V}\cdot \text {s}$ </tex-math></inline-formula> , a minor drain-induced barrier lowering (DIBL) of 41.5 mV/V, a negligible channel length shrinking ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\sf \Delta {L}$ </tex-math></inline-formula> ) of 47 nm and a record-low <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${R} _{\text {SD}}$ </tex-math></inline-formula> of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$0.86~\sf \Omega \cdot \text {cm}$ </tex-math></inline-formula> among self-aligned (SA) transistors. Such remarkable scalability and manufacturing capability pave a new cost-effective way for high integration-density oxide electronics.