A Low-Spur and Low-Jitter Fractional- <i>N</i> Digital PLL Based on an Inverse-Constant-Slope DTC and FCW Subtractive Dithering
Simone M. Dartizio, Francesco Tesolin, Giacomo Castoro, Francesco Buccoleri, Michele Rossoni, Dmytro Cherniak, Carlo Samori, Andrea L. Lacaita, Salvatore Levantino
Abstract
This work presents a low-spur and low-jitter fractional- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$N$ </tex-math></inline-formula> digital phase-locked loop (PLL). To reduce the fractional spurs caused by the non-linearity of the digital-to-time converter (DTC), two novel solutions are introduced. First, the inverse-constant-slope DTC achieves high-linearity, thanks to its immunity to channel-length modulation and non-linear parasitic capacitances. Second, the frequency-control-word (FCW) subtractive dithering technique randomizes the quantization error of the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\Delta \Sigma $ </tex-math></inline-formula> modulator driving the PLL divider ratio without requiring an increased DTC dynamic range and pushing the fractional spurs outside the PLL bandwidth. The prototype, implemented in a 28-nm CMOS process, has an active area of 0.33 mm2 and dissipates 17.2 mW. At fractional- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$N$ </tex-math></inline-formula> channels near 9.25 GHz, the measured in-band fractional spurs and the rms jitter are below −70 dBc and 77 fs, respectively, leading to a jitter-power figure of merit of −249.9 dB.