Capacitor-less, Long-Retention (>400s) DRAM Cell Paving the Way towards Low-Power and High-Density Monolithic 3D DRAM
Attilio Belmonte, Hyungrock Oh, Nouredine Rassoul, Gabriele Luca Donadio, Jérôme Mitard, Harold Dekkers, Romain Delhougne, Subhali Subhechha, Adrian Chasin, Michiel J. van Setten, Luka Ključar, Ming Mao, Harinarayanan Puliyalil, Murat Pak, Lieve Teugels, D. Tsvetanova, Kaustuv Banerjee, Laurent Souriau, Zs. Tôkei, L. Goux, Gouri Sankar Kar
Abstract
We report for the first time a fully 300-mm stacking-compatible capacitor-less DRAM cell with >400s retention time by integrating two IGZO-TFTs in a 2T0C configuration. We optimize the single IGZO-TFT performances by engineering the materials surrounding the IGZO layer and the transistor layout parameters. We thus introduce a novel IGZO-TFT device and demonstrate a scaled transistor (W = 70 nm, L = 45 nm) with optimal V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> reproducibility on 300-mm wafers. By integrating the IGZO-TFTs in a 2T0C configuration, we systematically assess reproducible long retention time for different transistor dimensions, thanks to the extremely low extracted IGZO-TFT off-current (~3x10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-19</sup> A/μm).