A 112-Gb/s PAM-4 Long-Reach Wireline Transceiver Using a 36-Way Time-Interleaved SAR ADC and Inverter-Based RX Analog Front-End in 7-nm FinFET
Jay Im, Kevin Zheng, Chuen-Huei Adam Chou, Lei Zhou, J. W. Kim, Stanley Chen, Y. Wang, Hao-Wei Hung, Kee Hian Tan, Winson Lin, Arianne Roldan, Declan Carey, Ilias Chlis, Ronan Casey, Ade Bekele, Ying Cao, David Mahashin, Hongshik Ahn, Hongtao Zhang, Yohan Frans, Kyung Won Chang
Abstract
A 36-way time-interleaved 56-GS/s 7-bit ADC is designed to realize 112-Gb/s pulse-amplitude modulation (PAM-4) transceiver in a 7-nm FinFET CMOS. The receiver analog front-end stages and the ADC track-and-hold (T/H) buffers are implemented using inverter-based Gm/inverse-Gm-load cells. A distributed inductor peaking network and multi-phase clock calibration is implemented in the quarter-rate transmitter. The transceiver achieves <; 1E-8 pseudorandom binary sequence (PRBS)-31 PAM-4 bit error rate (BER) over a channel with 37.5-dB loss at 28 GHz while dissipating 602 mW per channel, excluding DSP.