Endurance Improvement of Si FeFET by a Fully CMOS-Compatible Process: Insertion of HfO<sub> <i>x</i> </sub> at Hf<sub>0.5</sub>Zr<sub>0.5</sub>O<sub>2</sub>/SiO<sub> <i>x</i> </sub> Interface to Suppress Oxygen Vacancy Generation
Junshuai Chai, Hao Xu, Jinjuan Xiang, Yuanyuan Zhang, Shujing Zhao, Fengbin Tian, Jiahui Duan, Kai Han, Xiaolei Wang, Jun Luo, Wenwu Wang, Tianchun Ye
Abstract
This work investigates the endurance characteristic of Si FeFET with Hf0.5Zr0.5O2 ferroelectric. A fully CMOS-compatible method is shown to improve endurance: insertion of the thin HfOx layer (~2–5Å) at the Hf0.5Zr0.5O2/SiOx interface. The ab initio calculations prove that the HfOx insertion can increase the formation energies of oxygen vacancies and suppress their generation in the gate stacks and, consequently, improve the endurance. This method paves a possible path to improve the endurance of Si FeFET.
Topics & Concepts
Materials scienceOptoelectronicsFerroelectricitySiliconCMOSProcess (computing)Layer (electronics)Electronic engineeringElectrical engineeringNanotechnologyComputer scienceEngineeringDielectricOperating systemFerroelectric and Negative Capacitance DevicesSemiconductor materials and devicesMXene and MAX Phase Materials