Variability and Energy Consumption Tradeoffs in Multilevel Programming of RRAM Arrays
Eduardo Pérez, Mamathamba Kalishettyhalli Mahadevaiah, Emilio Pérez-Bosch Quesada, Christian Wenger
Abstract
Achieving a reliable multilevel programming operation in resistive random access memory (RRAM) arrays is still a challenging task. In this work, we assessed the impact of the voltage step value used by the programming algorithm on the device-to-device (DTD) variability of the current distributions of four conductive levels and on the energy consumption featured by programming 4-kbit HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> -based RRAM arrays. Two different write-verify algorithms were considered and compared, namely, the incremental gate voltage with verify algorithm (IGVVA) and the incremental step pulse with verify algorithm (ISPVA). By using the IGVVA, a main tradeoff has to be considered since reducing the voltage step leads to a smaller DTD variability at the cost of a strong increase in energy consumption. Although the ISPVA cannot reduce the DTD variability as much as the IGVVA, its voltage step can be decreased in order to reduce the energy consumption with almost no impact on the DTD variability. Therefore, the final decision on which algorithm to employ should be based on the specific application targeted for the RRAM array.