Hot Carrier Degradation in Cryo-CMOS
Wriddhi Chakraborty, Uma Sharma, Suman Datta, Souvik Mahapatra
Abstract
28nm Gate First High-K Metal Gate (GF-HKMG) technology is analyzed for Hot-Carrier Degradation (HCD) under varying gate/drain (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">G</sub> /V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">D</sub> ) bias and temperature (T: 300K to 77K). A compact model is used to partition measured threshold voltage shift (ΔV <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> ) into interface trap generation due to pure HCD (ΔV <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">IT-HC</sub> ), Bias Temperature Instability (BTI, ΔV <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">IT-BT</sub> ), and electron/hole trapping (ΔV <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ET</sub> /ΔV <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">HT</sub> ) subcomponents. The relative importance of the subcomponents is analyzed for varying T. Although pure HCD dominates under Cryo-CMOS operation, the T dependence is shown to be different for Si NMOS and SiGe PMOS FETs. Finally, the impact on the circuit (RO: Ring Oscillator) operation is analyzed.