Analysis of Negative Differential Resistance and RF/Analog Performance on Drain Engineered Negative Capacitance Dual Stacked-Source Tunnel FET
K. Vanlalawmpuia, Aditya Medury
Abstract
In this article, we systematically investigate the impact of ferroelectric (FE) layer thickness ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${t}_{{\text {FE}}}$ </tex-math></inline-formula> ) on the electrical parameters of a negative capacitance dual stacked-source tunnel field-effect transistor (NCDSS-TFET) using TCAD simulator. The increase in <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${t}_{{\text {FE}}}$ </tex-math></inline-formula> leads to higher <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${I}_{ \mathrm{\scriptscriptstyle ON}}/{I}_{ \mathrm{\scriptscriptstyle OFF}}$ </tex-math></inline-formula> current ratio and better subthreshold swing (SS) with negligible hysteresis. However, increasing FE layer thickness also introduces negative differential resistance (NDR) which is undesirable for analog circuit applications. The NCDSS-TFET device is further optimized to eliminate NDR effects by engineering the drain. The analog/RF performance of the drain-engineered NCDSS-TFET such as transconductance ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${g}_{\text {m}}$ </tex-math></inline-formula> ), output conductance ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${g}_{\text {d}}$ </tex-math></inline-formula> ), intrinsic gain ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${g}_{\text {m}}/{g}_{\text {d}}$ </tex-math></inline-formula> ), cutoff frequency ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${f}_{\text {T}}$ </tex-math></inline-formula> ), and intrinsic delay ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\tau $ </tex-math></inline-formula> ) is investigated. Analysis reports that the analog/RF parameters are improved by increasing the drain underlap length, thus ensuring the drain-engineered NCDSS-TFET suitable for high-performance and ultralow power analog applications.