Investigation of Optimal Architecture of MoS<sub>2</sub> Channel Field-Effect Transistors on a Sub-2 nm Process Node
Jihun Park, Hanggyo Jung, Wookyung Kwon, Gunhee Choi, Jeesoo Chang, Jongwook Jeon
Abstract
In this work, performance comparison of various architectures of field-effect transistors (FETs) introduced with transition metal dichalcogenide (TMDC) MoS 2 channels, which is attracting attention as one of the technologies that will enable beyond-silicon technology, was performed. By performing circuit-level benchmark for dynamic logic circuit operation in sub-2 nm dimension, it is observed that the optimal FET structure differs according to MoS 2 layer numbers. When two or more multilayer MoS 2 is applied to a double-gate and multistacked channel FET structure, the capacitance increases due to the increase in structure complexity, but the improvement of the current is greater, and the circuit operation speed increases. It is similar to the scaling-down trend of silicon-based FETs. However, in the case of monolayer MoS 2, a simple single-gate planar FET structure shows optimal circuit characteristics, which is analyzed to be due to the excellent short-channel effect immunity of the monolayer MoS 2 channel and small parasitic capacitance. Layout effects such as fan-out numbers and wiring load in integrated logic circuits were also investigated in various MoS 2 -FET structures. In addition, reliability analysis was performed through electrothermal simulation of thermal issues related to the multigate transistor structure.