Design and Analysis of Improved Phase-Transition FinFET Utilizing Negative Capacitance
Sameer Yadav, Pranshoo Upadhyay, Bhaskar Awadhiya, P. N. Kondekar
Abstract
Phase transition FinFET (PT-FinFET) is an emerging steep slope device that utilizes phase transition material (PTM) at the source of the host FinFET to achieve steep switching and boost <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${I}_{ \mathrm{\scriptscriptstyle ON}}/{I}_{ \mathrm{\scriptscriptstyle OFF}}$ </tex-math></inline-formula> ratio compared to conventional transistors. Due to nonzero <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\rho _{\text {MET}}$ </tex-math></inline-formula> of the assisting PTM, PT-FinFET suffers from low <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${I}_{ \mathrm{\scriptscriptstyle ON}}$ </tex-math></inline-formula> as compared to baseline FinFET. To address this issue, we propose, analyze, and mathematically justify a device design exhibiting enhanced subthreshold swing (SS), <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${I}_{ \mathrm{\scriptscriptstyle ON}}$ </tex-math></inline-formula> and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${I}_{ \mathrm{\scriptscriptstyle OFF}}$ </tex-math></inline-formula> by exploiting a negative capacitance material at the gate of the PT-FinFET. In the proposed model, critical thickness ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${t}_{\textit {fe}}$ </tex-math></inline-formula> ) of 3 nm for negative capacitance material was achieved. In comparison with the baseline FinFET and negative capacitance PT-FinFET, the proposed device (NC-PT-FinFET) is able to improve <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${I}_{ \mathrm{\scriptscriptstyle ON}}/{I}_{ \mathrm{\scriptscriptstyle OFF}}$ </tex-math></inline-formula> ratio by 3.02 and 2.94 decades, respectively. Furthermore, SS of nearly 10 mV/decade is achieved over 4 decades of drain current with minimum value of 6.8 mV/decade for <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${t}_{\textit {fe}}\,\,= {3}$ </tex-math></inline-formula> nm.