Multi-Bit Compute-In Memory Architecture Using a C-2C Ladder Network
Dinesh Kushwaha, Jaya Kumar Abotula, Rajat Kohli, Jwalant Mishra, Sudeb Dasgupta, Anand Bulusu
Abstract
This brief uses the capacitive charge coupling method to present a multi-bit SRAM-based compute-in-memory (CIM) architecture in the analog domain. The proposed architecture consists of a 64×64 9T1C SRAM array performing 1024 MAC operations between input activation (4-bit) and weight (4-bit) in a cycle, and an optimized 4-bit Flash ADC is used for converting the analog MAC into digital output. This work achieves a throughput of 455 GOPS and an energy efficiency of 1012 TOPS/W at 222 MHz, maintaining a very high signal margin of 54 mV. The achieved inference accuracy is 98% for MNIST and 86 % for the CIFAR-10 data set. This proposed work is implemented on a 28 nm CMOS Technology node at 0.9 V supply.