Fundamental Issues in VNAND Integration Toward More Than 1K Layers
Jeehoon Han, Seogoo Kang, Kyungdong Kim, Jae Hoon Jang, Jaihyuk Song
Abstract
In a vertical NAND (VNAND) integration, which has the characteristic of increasing height, several major problems caused by height will be pointed out, and general approaches so far to solve them and new directions for the future will be presented. Solutions to minimize the mold height at the same number of layers or bits, lessen the manufacturing cost caused by individually drilling various types of holes in the mold, increase the cell current of long channels in the height direction, and reduce the ratio of areas other than cell array will be discussed.
Topics & Concepts
NAND gateMoldComputer scienceVertical integrationDrillingCurrent (fluid)Mechanical engineeringEngineeringElectrical engineeringMaterials scienceLogic gateComposite materialLawPolitical scienceIntegrated Circuits and Semiconductor Failure AnalysisSemiconductor materials and devicesThin-Film Transistor Technologies