An Outphase-Interleaved Switched-Capacitor Hybrid Buck Converter With Relieved Capacitor Inrush Current and C_OUT-Free Operations

Abstract

This article presents an efficient buck converter design using the proposed outphase-interleaved hybrid switched-capacitor (OISC) topology. The outphase-interleaved switched-capacitor (SC) cells significantly extend the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$C_{\mathrm {F}}$ </tex-math></inline-formula> charge-balancing phase without disturbing the inductor volt-second balance (VSB), while doubling the effective inductor switching frequency for reduced current ripple. As a result, it addresses the intrinsic issue of sharply increased flying capacitor ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$C_{\mathrm {F}}$ </tex-math></inline-formula> ) inrush current in existing SC dual-/multi-path (DP/MP) hybrid buck converters under extreme duty ratios, resolving the tradeoff between SC cell conduction loss and inductor dc current ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$I_{L,\mathrm {dc}}$ </tex-math></inline-formula> ) reduction capability. The proposed topology attains three key advantages: 1) relived <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$C_{\mathrm {F}}$ </tex-math></inline-formula> hard-charging-induced inrush current; 2) reduced <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$I_{L,\mathrm {dc}}$ </tex-math></inline-formula> ; and 3) power stage normal operation without relying on an output capacitor <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$(C_{\mathrm {OUT}})$ </tex-math></inline-formula> , resulting in improved conversion efficiency and power density. To enhance the overall power density and mitigate gate-driving path ringing, we propose an area-efficient fully ON-chip gate-driving scheme with a shared charge pump (CP), ensuring proper operations with all-NMOS power switches. Fabricated in a 180-nm CMOS process with 7.63 mm2 chip area, the converter achieves a peak conversion efficiency of 97.3% and an overall peak current density of 585 mA/mm3 at 90.1% efficiency. Supporting a load current ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$I_{\mathrm {LOAD}}$ </tex-math></inline-formula> ) from 0.05 to 3.1 A, it converts 1.8–3.3 V input to 0.8–1.8 V output. Measured output voltage ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$V_{\mathrm {OUT}}$ </tex-math></inline-formula> ) ripple is ~3.3% of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$V_{\mathrm {OUT}}$ </tex-math></inline-formula> dc under 3.1 A <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$I_{\mathrm {LOAD}}$ </tex-math></inline-formula> with zero <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$C_{\mathrm {OUT}}$ </tex-math></inline-formula> .

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