Sub-10-nm Diameter Vertical Nanowire p-Type GaSb/InAsSb Tunnel FETs
Yanjie Shao, Jesús A. del Alamo
Abstract
In this letter, we report the realization of sub-10-nm diameter vertical nanowire (VNW) p-type tunnel FETs (TFETs). Using a broken-band GaSb/InAsSb heterostructure design and a top-down fabrication approach, we demonstrate a 9-nm diameter VNW TFET with excellent on-state characteristics featuring a peak transconductance of 90 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{S}/\mu \text{m}$ </tex-math></inline-formula> at <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$V_{{\text {ds}}} = -0.3$ </tex-math></inline-formula> V. The same device exhibits a minimum linear subthreshold swing of 225 mV/dec at <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$V_{\text {ds}} = -0.05$ </tex-math></inline-formula> V. Our p-type GaSb/InAsSb TFETs exhibit clear negative differential resistance at room temperature, with a peak-to-valley current ratio over 3. The excellent device performance of these devices bodes well for the viability of GaSb-based complementary TFETs in future ultra-scaled logic technologies.