A 1-to-112Gb/s DSP-Based Wireline Transceiver with a Flexible Clocking Scheme in 5nm FinFET

A. Varzaghani, Bardia Bozorgzadeh, Jack Lam, Ankush Goel, Xiaobin Yuan, Mohamed Elzeftawi, Mehran Izad, Sudipta Sarkar, Alberto Baldisserotto, Seong-Ryong Ryu, Steven Mikes, Jeffrey Hwang, Varun Joshi, Shahrzad Naraghi, Darshan Kadia, Mohammad Ranjbar, Paul Lee, Dimitri Loizos, Sotirios Zogopoulos, Shwetabh Verma, S. Sidiropoulos

20222022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)13 citationsDOI

Abstract

A low-power transceiver using a flexible clocking scheme is presented to enable the entire range of rates for Ethernet and PCIe applications. In addition, each lane can independently support any data rate within the same protocol. Implemented in 5nm FinFET, the quad transceiver occupies 1806×825μm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and achieves a total power efficiency of 5.6pJ/b per lane including analog and DSP at 112Gb/s.

Topics & Concepts

TransceiverWirelineEthernetPCI ExpressDigital signal processingComputer scienceScheme (mathematics)Embedded systemPower (physics)Computer hardwareApplication-specific integrated circuitElectronic engineeringEngineeringField-programmable gate arrayWirelessTelecommunicationsPhysicsQuantum mechanicsMathematical analysisMathematicsLow-power high-performance VLSI designInterconnection Networks and SystemsSemiconductor materials and devices