A 260-GHz Four-Way Phase Compensated CMOS Frequency Multiplier Chain
Ruibing Dong, Shinsuke Hara, Satoru Tanoi, Tatsuo Hagino, Issei Watanabe, Mohamed H. Mubarak, Akifumi Kasamatsu
Abstract
A novel × 6 frequency multiplier chain with a center frequency of 260 GHz is developed in 40 nm CMOS and measured through this work. The multiplication is accomplished through an × 3 frequency multiplier followed by a doubler successive stage. A four-way signal combiner is employed to enhance the output power, whereas phase shifters are dedicated for compensating the possible phase deviations between the different combined ways, and consequently maintain the combining efficiency. For further output power boosting, the output matching network of 260-GHz frequency doubler is optimized, and a stacked amplifier with 11.5 dBm is employed as a driving amplifier. The multiplier has been fabricated and a peak output power of 3.0 dBm is measured at 260 GHz with a 3-dB bandwidth of 17 GHz.