A Low-Voltage-Driven High-Voltage SRAM Pixel Circuit for Power Reduction in a Digital Micro-Display Panel
Je-Kwang Cho, Minsu Jeong
Abstract
A new SRAM-based pixel circuit is presented for use in a high-voltage digitally-driven pixel array in a micro-display panel. The pixel circuit is based on the standard 6T SRAM structure, but uses two more transistors of which gate dc-bias is controlled to adjust the pull-up strength of the inverters in the SRAM. This allows the pixel circuit to be operated with low-voltage row- and column-line signals while holding the stored logic in a high-voltage level. As a result, power and area of the pixel driving circuits are greatly reduced. The added two transistors do not necessitate area overhead if the pixels are to be individually separated with rectangular shape, which is true in many cases. To verify proper operation and power reduction efficacy of the proposed SRAM pixel circuit, a simple $100\times 200$ digital pixel array, together with row- and column-line drivers, is implemented using a 0.13-$\mu \text{m}$ CMOS technology and 1.5-V/3.3-V supplies. The measurement results show that, with the optimum bias for the two added transistors, total power dissipation including pixel array and driver power can be reduced by about as much as 78 %, which is very close to the theoretical limit of 79 % (= (1.5/3.3) <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> ).