An Efficient Design of 8 * 8 Wallace Tree Multiplier Using 2 and 3-Bit Adders
M Sakthimohan, J. Deny
Topics & Concepts
Multiplier (economics)AdderVHDLArithmeticComputer scienceVery-large-scale integrationBooth's multiplication algorithm8-bitComputer hardwareMathematicsComputer architectureParallel computingEmbedded systemField-programmable gate arrayTelecommunicationsMacroeconomicsEconomicsLatency (audio)Low-power high-performance VLSI designVLSI and FPGA Design TechniquesAdvancements in Semiconductor Devices and Circuit Design